1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device comprising a high-speed analog circuits connecting to multiple-power supplies and specific structure capable of reducing cross talk originating in these analog circuits.
This application is based on Patent Application No. Hei 8-3052293 filed in Japan, the content of which is incorporated herein by reference.
2. Background Art
In general, it is essential to prevent cross talk in a semiconductor device comprising analog circuits. Cross-talk is a phenomenon in which the original signal to be processed is disturbed by random signals propagating through parasitic paths by parasitic resistance or by parasitic capacitance. Cross talk originates from paths through various parts of the device, such as, wiring, the epitaxial layers, the buried layers, and the substrate.
In order to reduce cross talk through wiring, a conventional method was elaborated in which a power supply was divided into multiple power supplies which are independent of each other. An example for preventing cross talk through the substrate is disclosed in Japanese Patent Application, First Publication, No. 63-181346. This conventional example, as illustrated in FIG. 6, reduces cross talk by stabilizing a potential of a conductive layer 721 at an earth potential of the semiconductor device by connecting the conductive layer 721 with a conductive earth-contact layer 724 formed under the buried layer 723 which is formed below regions consisting of a base region 722, an emitter region 717, and a collector region 716 which compose a transistor.
In analog circuits composed of bipolar transistors, the need to integrate elements to higher density has lead to the use not only of LOCOS (Local Oxidation of Silicon) film but also of a trench for separation of elements. An example of such separation of elements by trenches is shown in FIGS. 5A and 5B, in which two bipolar transistors 108 and 109 are separated by respective trenches 104 and 105. This conventional device is an example, in which the width of trench is made narrower in response to the need for integrating elements to higher density, and the first transistor 108 is used as a circuit for processing signals with large amplitude, such as the input and output buffers, while the second transistor 109 is used as a circuit for processing signals with small amplitude like a first stage amplifier.
In the above example, however, cross talk is generated between a first n-type buried layer 202 and a second n-type buried layer 203 due to parasitic capacitance between the first n-type buried layer 202 and a p-type semiconductor substrate 200 including trenches 104 and 105, and between the p-type semiconductor substrate 200 and the second n-type buried layer 203, and also due to the resistance of the p-type semiconductor substrate 200. This is because the parasitic resistance is decreased due to the narrowed space between two elements and the parasitic capacitance is increased due to element separation by the trench.
Cross talk through the substrate can be reduced by applying the conventional method disclosed in the above Japanese Patent Application to the above structure. That is, cross talk through the p-type semiconductor substrate 200 can be reduced, as shown in FIG. 7, by forming an earth-contact layer 724 under n-type buried layer 202 and 203, and by stabilizing the potential of the earth contact layer 725 at the earth potential of the semiconductor device.
However, it was found that the above conventional structure have problems in terms of reduction or elimination of cross talk.
The first problem is that such conventional structures are not effective for reducing cross talk in a particular semiconductor device, in which a power supply is separated into multiple power supplies for respective circuit blocks. The reason is that, the earth contact layer 724 is common for the whole substrate area so that a fluctuation of an potential or a voltage of, for example, an output circuit has affects on the functional operation of the other circuit on the same chip through the earth-contact layer 724. This effect appears markedly, for example, in the amplifier circuit which processes small signals.
The second problem is that the above conventional structure for reducing cross talk is not suitable for high speed operation of transistors. The reason is that, in the case of a npn-type transistor, since the first and second buried layers 202 and 203 are doped in high concentration, the parasitic capacitance between these buried layers 202 and 203 and the p-type high concentration earth-contact layer 724 increases, and, furthermore, since the conductive layers 721 formed on side walls of respective trenches are connected to the earth-contact layer 724, and since each transistor faces the conductive layer 721 across a thin insulating layer, the capacitance of the transistor against the substrate becomes extremely high.